The present disclosure generally relates to process control methods, and particularly to methods of controlling semiconductor manufacturing processes employing alignment data generated during lithographic processing steps.
Various processing steps such lithographic exposure and development, deposition, etching, and planarization are employed in semiconductor manufacturing. Most processes that add material, such as deposition, or remove material, such as etch and planarization, alter the distribution of material on a substrate. The alteration in the distribution of the material on the substrate causes structural changes in the substrate by deforming the substrate.
Stress liners and stress-generating embedded elements are intended to introduce stress into a substrate, which inevitably causes global bowing of the substrate. In addition to such elements that are intended to introduce stress, deposition, etch, or planarization of any material on a substrate typically introduces some degree of deformation in the substrate.
The pattern and the degree of deformation of a substrate depend on the type of processing and the tool employed to effect the processing. For example, low temperature chemical vapor deposition (LPCVD) tools tend to have a thickness pattern in which the center region and regions in the immediate vicinity of rail marks have a lesser thickness than the rest of the substrate. Etch tools may have an inherent center-to-edge nonuniformity in the amount of material removed from the substrate. Chemical mechanical planarization (CMP) tools may have tool-specific non-uniformity in the removal rate so that the remaining material on a substrate tends to be thick or thin in a particular region relative to a wafer notch or other global alignment features.
In order to maintain a high-yield stable manufacturing line, process deviations in the various tools employed in a manufacturing line need to be detected promptly, and any process deviations need to be corrected as quickly as possible.